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Assembly Hall of Shame (github.com)

434 points by piotrgrabowski · 19 days ago · 112 comments on HN

Article summary

The Assembly Hall of Shame is a research project that aims to find the slowest possible single instructions on various CPU architectures. The project uses a variety of strategies to slow down instructions, including using subnormals, MMIO, and PCIe fabric. The current champion is the fxrstor64 instruction on an AMD Ryzen 7 5800H, which takes approximately 62 seconds to execute. The project provides a leaderboard of the slowest instructions on different architectures.

Main themes

  • CPU performance optimization
  • Instruction latency analysis
  • MMIO and PCIe fabric
  • Subnormals and floating-point operations
  • Computer architecture

What commenters say

  • Some commenters appreciate the project as a resource for performance deoptimization and a showcase of creative strategies to slow down instructions.
  • The project highlights the trade-off between latency and throughput in computer performance, with some arguing that added layers of abstraction have increased latency.
  • There is disagreement about the perception of latency, with some arguing that humans can perceive differences in latency as small as 50ms, while others claim that 10ms is the limit for interactive response.
  • Some commenters note that the project's findings may not be applicable to other architectures, and that the winning strategies may be specific to certain CPU designs.
  • The discussion also touches on the topic of computer responsiveness and whether it has improved or worsened over time, with some arguing that updates have not significantly impacted responsiveness.
  • There is a humorous suggestion that using the nop instruction for everything could be a viable approach, as it is essentially 'no code'.
  • Some commenters are interested in exploring the project's findings on other architectures, such as POWER, to see if different strategies would emerge.
  • The project's approach is seen as a creative way to test the limits of CPU performance and to identify potential bottlenecks in computer architecture.