The article presents a repository containing source code for a GEMM and deep learning hardware accelerator system that uses algebraic enhancements to reduce the number of multiplications required for matrix multiplication. The system achieves up to 3× faster CNN inference and 2× higher mults/multiplier/clock cycle compared to state-of-the-art accelerators. The proposed systolic array architectures can be seamlessly integrated into existing accelerator systems to increase performance per MAC unit. The repository includes a compiler, synthesizable SystemVerilog accelerator RTL, and simulation scripts.